1. Field of the Invention
Example embodiments of the present invention relate to a transistor in a semiconductor device, an etchant and methods of forming the same. Other example embodiments relate to a transistor having a metal nitride layer pattern, an etchant and methods of forming the same.
2. Description of the Related Art
In order to obtain a higher speed semiconductor device, the thickness of a gate insulating layer in a transistor may be reduced. Prior to reducing the thickness, the gate insulating layer may be formed with a higher dielectric constant (high-k) material on the semiconductor substrate in order to maintain electrostatic capacitance of the gate insulating layer. Further, a gate electrode may be formed in the transistor using a metal nitride layer and/or a poly-silicon layer stacked on the gate insulating layer. The metal nitride layer may be used for reducing and/or preventing depletion of charges in the poly-silicon layer during the driving of the transistor.
The gate electrode may be formed by performing an etching process on a predetermined region of the poly-silicon layer and/or the metal nitride layer. The etching process may use a plasma etchant to etch the poly-silicon layer and/or the metal nitride layer.
Using a plasma etchant on the metal nitride layer may cause etching damage to the gate insulating layer and/or the semiconductor substrate. In addition, the etching process may remove a portion of the semiconductor substrate by etching the gate insulating layer exposed by the gate electrode. This may cause deterioration in electrical characteristics of the transistor.
The prior art acknowledges a method of etching a tantalum nitride layer in a high density plasma. The tantalum nitride layer may be exposed to the high density plasma. The tantalum nitride layer may be formed between a dielectric layer and a photoresist pattern stacked on the semiconductor substrate. The high density plasma may be formed using a source gas including a primary etchant gas and/or a profile-control additive. The tantalum nitride layer may be etched using the high density plasma to form a tantalum nitride gate electrode on the dielectric layer.
The conventional methods may cause plasma damage to the dielectric layer and/or the semiconductor substrate during the formation of the gate electrode. In order to reduce the plasma damage, additional unit processes may be needed. However, additional unit processes may increase the cost of fabricating the gate electrode on the semiconductor substrate.